The present invention relates to a semiconductor device equipped with a capacitor including a capacitor dielectric film made from a dielectric film with a large dielectric constant (hereinafter referred to as a highly dielectric film) or a ferroelectric film, and method and system for fabricating the same.
In accordance with recent trend toward a high operation speed and small power consumption of microcomputers and the like, consumer electronic equipment are highly developed, and semiconductor elements included in semiconductor devices used in the consumer electronic equipment have been rapidly refined.
As a result, unwanted radiation, that is, electromagnetic wave noise caused in electronic equipment, has become a serious problem. As means for reducing the unwanted radiation, attention is paid to a technique to involve, in a semiconductor integrated circuit device, a capacitor having large capacity and including a capacitor dielectric film of a highly dielectric film or a ferroelectric film.
Furthermore, in accordance with development of higher integration of a dynamic RAM, a technique to use a highly dielectric film or a ferroelectric film as a capacitor dielectric film of a capacitor instead of a conventionally used oxide or nitride of silicon is now widely studied.
Moreover, for the purpose of realizing practical use of a nonvolatile RAM capable of operating at a low voltage and reading or writing at a high speed, a ferroelectric film with a spontaneous polarization characteristic is now earnestly studied and developed.
Accordingly, it is significant to develop a method for realizing higher integration of a semiconductor device without degrading characteristics of a capacitor.
Now, a conventional method of fabricating a semiconductor device will be described with reference to FIGS. 11A through 11C, 12A and 12B.
First, as is shown in FIG. 11A, after forming an isolation region 11 and a gate electrode 12 of an FET on a semiconductor substrate 10, impurity diffusion layers and the like (not shown) of the FET are formed in a surface portion of the semiconductor substrate 10, and an insulating film 13 is deposited to cover the isolation region 11 and the gate electrode 12. Thereafter, on a portion of the insulating film 13 above the isolation region 11, a capacitor lower electrode 14 of a platinum film or the like, a capacitor dielectric film 15 of a highly dielectric film or a ferroelectric film and a capacitor upper electrode 16 of a platinum film or the like are formed. The capacitor lower electrode 14, the capacitor dielectric film 15 and the capacitor upper electrode 16 together form a capacitor.
Next, as is shown in FIG. 11B, after forming a first protection film 17 for covering the capacitor, a contact hole 18 of the FET is formed in the insulating film 13 and a contact hole 19 of the capacitor is formed in the first protection film 17. Then, a metal film such as a titanium film and an aluminum alloy film is deposited over the insulating film 13 and the first protection film 17, and the metal film is patterned into a first interconnection layer 20 connected to the impurity diffusion layer of the FET or the capacitor upper electrode 16. Thereafter, the first interconnection layer 20 is subjected to a heat treatment.
Then, as is shown in FIG. 11C, by plasma tetraethylorthosilicate (hereinafter referred to as TEOS) CVD, an interlayer insulating film (plasma TEOS film) 21 of a silicon oxide film is deposited over the first interconnection layer 20 and the capacitor. In consideration of planarization by reflow, the interlayer insulating film 21 is formed so as to have a thickness of approximately 1 μm or more in a portion above the first interconnection layer 20 on the capacitor upper electrode 16.
Next, after planarizing the interlayer insulating film 21, a contact hole is formed in the interlayer insulating film 21, and a second interconnection layer 22 connected to the first interconnection layer 20 is formed on the interlayer insulating film 21 as is shown in FIG. 12A.
Then, as is shown in FIG. 12B, a second protection film 23 is deposited on the interlayer insulating film 21 so as to cover the second interconnection layer 22.
However, since the interlayer insulating film 21 is formed from the plasma TEOS film in the conventional structure, the interlayer insulating film 21 applies merely small stress to the capacitor and tends to be compressive. Accordingly, there arises a problem that the capacitor dielectric film 15 cannot sufficiently attain spontaneous planarization, and hence, the capacitor cannot attain good characteristics.
Therefore, the present inventors have proposed, in Japanese Patent Publication No. 2846310, a technique to use, instead of the plasma TEOS film, a silicon oxide film formed by TEOS-O3 CVD (hereinafter referred to as the TEOS-O3 film) as the interlayer insulating film 21.
When the TEOS-O3 film is used as the interlayer insulating film 21, stress applied to the capacitor can be increased, so as to improve the characteristics of the capacitor.
The use of the TEOS-O3 film as the interlayer insulating film, however, causes other problems as follows: Defects such as holes are locally formed in the interlayer insulating film of the TEOS-O3 film; and the growth rate of the TEOS-O3 film is varied depending upon the kind of underlying film.
Such problems lead to quality degradation of a semiconductor integrated circuit device, and in addition, the characteristics of the capacitor cannot be improved because stress cannot be uniformly applied to the capacitor.